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motorola semiconductor technical data dsp56012/d rev. 0, 09/98 ? motorola, inc., 1998 advance information dsp56012 24-bit dvd digital signal processor the dsp56012 is a high-performance programmable digital signal processor (dsp) developed for digital versatile disc (dvd), high-definition television (hdtv), and advanced set-top audio decoding. the dsp56012 is optimized with audio-specific peripherals and customized memory configuration, and may be programmed with motorolas certified software for dolby ac-3 5.1 channel surround, dolby pro logic, and mpeg1 layer 2. these applications use motorolas 24- bit dsp56000 architecture and are the highest quality solutions available. flexible peripheral modules and interface software allow simple connection to a wide variety of video/system decoders. in addition, the dsp56012 offers switchable memory space configuration, a large user- definable program rom and two independent data rams and roms, a serial audio interface (sai), a serial host interface (shi), a parallel host interface (hi) with direct memory access (dma) for communicating with other processors, dedicated i/o lines, an on-chip phase-locked loop (pll), an on-chip emulation (once ? ) port, and an on-chip digital audio transmitter (dax). figure 1-1 shows the functional blocks of the dsp56012. figure 1-1. dsp56012 block diagram y data memory x data memory program memory program control unit 24-bit dsp56000 core once tm port pll clock gen. 8 9 5 2 16-bit bus 24-bit bus data alu 24 24 + 56 ? 56-bit mac two 56-bit accumulators 4 irqa, irqb, nmi, reset 4 3 internal data bus switch address generation unit pab xab yab gdb pdb xdb ydb general purpose i/o (gpio) digital audio transmitter (dax) serial audio interface (sai) serial host interface (shi) parallel host interface (hi) 15 extal expansion area program address generator program decode controller program interrupt controller aa1271
1-2 dsp56012 data sheet motorola content organization part 1 introduction to the dsp56012 refer to section 1.1 for information on this data sheet and on the dsp56012. 1.1 content organization this section outlines the information contained in this document. part 1, introduction to the dsp56012.......................................................................................... ....... 1-2 1.1, content organization ..................................................................................................... ....... 1-2 1.2, data conventions ......................................................................................................... ......... 1-3 part 2, features .............................................................................................................. ..................... 2-1 2.1, features of the digital signal processing core .................................................................... 2-1 2.2, features of the dsp56012 memory configuration .............................................................. 2-1 2.3, peripheral and support circuits .......................................................................................... .. 2-2 2.4, documentation ............................................................................................................ .......... 2-3 part 3, signal/connection descriptions........................................................................................ ...... 3-1 3.1, signal groupings......................................................................................................... .......... 3-1 part 4, specifications ........................................................................................................ .................. 4-1 4.1, introduction ............................................................................................................. .............. 4-1 4.2, maximum ratings.......................................................................................................... ....... 4-1 4.3, thermal characteristics .................................................................................................. ...... 4-2 4.4, dc electrical characteristics ............................................................................................ .... 4-2 4.5, ac electrical characteristics ............................................................................................ .... 4-3 4.6, internal clocks .......................................................................................................... ............ 4-3 4.7, external clock operation................................................................................................. ..... 4-4 4.8, phase-locked loop (pll) characteristics ........................................................................... 4-5 4.9, reset, stop, mode select, and interrupt timing ............................................................... 4-5 4.10, host interface (hi) timing .............................................................................................. ... 4-7 4.11, serial audio interface (sai) timing) ............................................................................... 4-12 4.12, serial host interface (shi) spi protocol timing ............................................................. 4-15 4.13, serial host interface (shi) i2c protocol timing ............................................................. 4-21 4.14, programming the serial clock .......................................................................................... 4- 22 4.15, general purpose input/output (gpio) timing................................................................. 4-27 4.16, digital audio transmitter (dax) timing........................................................................ 4-28 4.17, on-chip emulation (once) timing................................................................................. 4-29 part 5, packaging ............................................................................................................. ................... 5-1 5.1, pin-out and package information......................................................................................... 5 -1 5.2, tqfp package description ................................................................................................. .. 5-1 5.3, ordering drawings........................................................................................................ ........ 5-6 part 6, design considerations ................................................................................................. ........... 6-1 6.1, thermal design considerations............................................................................................ 6-1 6.2, electrical design considerations ......................................................................................... . 6-2 6.3, power consumption considerations ..................................................................................... 6-3 6.4, power-up considerations .................................................................................................. ... 6-4 6.5, host port considerations ................................................................................................. ..... 6-5 part 7, ordering information .................................................................................................. ............ 7-1
data conventions motorola introduction to the dsp56012 1-3 1.2 data conventions this data sheet uses the following conventions: ? overbar : used to indicate a signal that is active when pulled low (e.g., reset ). ? asserted means that a high true signal (i.e., an active high) is high or that a low true signal (i.e., an active low) is low. ? deasserted means that a high true signal is low or that a low true signal is high. please refer to the examples in table 1-1. table 1-1. data conventions signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol
1-4 dsp56012 data sheet motorola data conventions
features of the dsp56012 memory configuration motorola features 2-1 part 2 features 2.1 features of the digital signal processing core ? efficient, object-code compatible, 24-bit dsp56000 family dsp engine ? 47.5 million instructions per second (mips) with 21.05 ns instruction cycle at 95 mhz ? highly parallel instruction set with unique dsp addressing modes ? two 56-bit accumulators including extension byte ? parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) ? double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles ? 56-bit addition/subtraction in 1 instruction cycle ? fractional and integer arithmetic with support for multi-precision arithmetic ? hardware support for block-floating point fast fourier transforms (fft) ? hardware nested do loops ? zero-overhead fast interrupts (2 instruction cycles) ? pll-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2 i : i = 0 to 15), which reduces clock noise ? four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories 2.2 features of the dsp56012 memory configuration ? modified harvard architecture allows simultaneous access to program and data memories ? 15360 24-bit on-chip program rom 1 ? 4096 24-bit on-chip x data ram and 3584 24-bit on-chip x data rom 1 ? 4352 24-bit on-chip y data ram and 2048 24-bit on-chip y data rom 1 ? 256 24-bit on-chip program ram and 32 24-bit bootstrap rom ? as much as 2304 24 bits of x and y data ram can be switched to program ram, giving a total of 2560 24 bits of program ram table 2-1 lists the memory configurations of the dsp56012. 1. these roms may be factory programmed with data/program provided by the application developer. table 2-1. dsp56012 internal memory configurations memory type no switch (pea = 0, peb = 0) switch a (pea = 1, peb = 0) switch b (pea = 0, peb = 1) switch a+b (pea = 1, peb = 1) program ram 0.25k 1.0k 1.75k 2.5k x data ram 4.0k 3.25k 3.25k 2.5k y data ram 4.25k 4.25k 3.5k 3.5k program rom 15k 15k 15k 15k
2-2 dsp56012 data sheet motorola peripheral and support circuits 2.3 peripheral and support circuits ? sai includes: two receivers and three transmitters master or slave capability i 2 s, sony, and matsushita audio protocol implementations two sets of sai interrupt vectors ? shi features: single master capability spi and i 2 c protocols 10-word receive fifo support for 8-, 16- and 24-bit words. ? byte-wide parallel host interface with dma support capable of reconfiguration as 15 general purpose input/output (gpio) lines ? dax features one serial transmitter capable of supporting s/pdif, iec958, cp-340, and aes/ebu formats. ? eight dedicated, independent, programmable gpio lines ? on-chip peripheral registers memory mapped in data memory space ? once port for unobtrusive, processor speed-independent debugging ? software programmable pll-based frequency synthesizer for the core clock ? power saving wait and stop modes ? fully static, hcmos design from specified operating frequency down to dc ? 100-pin plastic thin quad flat pack (tqfp) surface-mount package ? 5 v power supply x data rom 3.5k 3.5k 3.5k 3.5k y data rom 2.0k 2.0k 2.0k 2.0k table 2-1. dsp56012 internal memory configurations memory type no switch (pea = 0, peb = 0) switch a (pea = 1, peb = 0) switch b (pea = 0, peb = 1) switch a+b (pea = 1, peb = 1)
documentation motorola features 2-3 2.4 documentation table 2-2 lists the documents that provide a complete description of the dsp56012 and are required to design properly with the part. documentation is available from a local motorola distributor, a motorola semiconductor sales office, a motorola literature distribution center, or through the motorola dsp home page on the internet (the source for the latest information). table 2-2. additional dsp56012 documentation document name description order number dsp56000 family manual detailed description of the 56000-family architecture and the 24-bit core processor and instruction set dsp56kfamum/ad dsp56012 users manual detailed description of memory, peripherals, and interfaces dsp56012um/ad dsp56012 technical data electrical and timing specifications; pin and package descriptions dsp56012/d
2-4 dsp56012 data sheet motorola documentation
signal groupings motorola signal/connection descriptions 3-1 part 3 signal/connection descriptions 3.1 signal groupings the input and output signals of the dsp56012 are organized into ten functional groups, as shown in table 3-1 and as illustrated in figure 3-1. table 3-1. dsp56012 functional signal groupings functional group number of signals detailed description power (v cc ) 13 table 3-2 ground (gnd) 17 table 3-3 pll 4 table 3-4 interrupt and mode control 4 table 3-5 host interface (hi) port b 15 table 3-6 serial host interface (shi) 5 table 3-7 serial audio interface (sai) 9 table 3-8 table 3-9 general purpose input/output (gpio) 8 table 3-10 digital audio transmitter (dax) 2 table 3-11 once port 4 table 3-12
3-2 dsp56012 data sheet motorola signal groupings figure 3-1. signals identified by functional group dsp56012 digital audio transmitter (dax) pll once? port power inputs: pll internal logic a d hi shi debug dsi dsck dso dr plock pcap pinit extal v ccp v ccq v cca v ccd v cch v ccs 4 serial audio interface (sai) rec0 rec1 tran0 tran1 tran2 1 2 3 grounds: pll internal logic a d hi shi gnd p gnd q gnd a gnd d gnd h gnd s 4 3 2 3 interrupt/ mode control moda/irqa modb/irqb modc/nmi reset host interface (hi) port h0Ch7 hoa0 hoa1 hoa2 hr/w hen horeq hack wsr sckr sdi0 sdi1 wst sckt sdo0 sdo1 sdo2 ado aci 8 2 4 serial host interface (shi) spi mode mosi ss miso sck hreq port b gpio pb0Cpb7 pb8 pb9 pb10 pb11 pb12 pb13 pb14 general purpose input/output (gpio) gpio0Cgpio7 8 hi i 2 c mode ha0 ha2 sda scl hreq non-debug os0 os1 dso dr
signal groupings motorola signal/connection descriptions 3-3 3.1.1 power 3.1.2 ground table 3-2. power inputs power name description v ccp pll power v ccp is v cc dedicated for phase-locked loop (pll) use. the voltage should be well-regulated, and the input should be provided with an extremely low impedance path to the v cc power rail. v ccp should be bypassed to gnd p by a 0.1 m f capacitor located as close as possible to the chip package. v ccq quiet power v ccq is an isolated power for the internal processing logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v cca a power v cca is an isolated power for sections of the internal chip logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccd d power v ccd is an isolated power for sections of the internal chip logic. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v cch host power v cch is an isolated power for the hi i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. v ccs serial host power v ccs is an isolated power for the shi i/o drivers. this input must be tied externally to all other chip power inputs. the user must provide adequate external decoupling capacitors. table 3-3. grounds ground name description gnd p pll ground gnd p is ground dedicated for pll use. the connection should be provided with an extremely low-impedance path to ground. v ccp should be bypassed to gnd p by a 0.1 m f capacitor located as close as possible to the chip package. gnd q internal logic ground gnd q is an isolated ground for the internal processing logic. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd a a ground gnd a is an isolated ground for sections of the internal logic. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors.
3-4 dsp56012 data sheet motorola signal groupings 3.1.3 phase-locked loop (pll) gnd d d ground gnd d is an isolated ground for sections of the internal logic. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd h host ground gnd h is an isolated ground for the hi i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. gnd s serial host ground gnd s is an isolated ground for the shi i/o drivers. this connection must be tied externally to all other chip ground connections. the user must provide adequate external decoupling capacitors. table 3-4. phase lock loop signals signal name type state during reset signal description plock output indeterminate phase locked plock is an output signal that, when driven high, indicates that the pll has achieved phase lock. after reset, plock is driven low until lock is achieved. note: plock is a reliable indicator of the pll lock state only after the chip has exited the reset state. during hardware reset, the plock state is determined by pinit and the current pll lock condition. pcap input input pll capacitor pcap is an input connecting an off-chip capacitor to the pll filter. connect one capacitor terminal to pcap and the other terminal to v ccp . if the pll is not used, pcap may be tied to v cc , gnd, or left floating. pinit input input pll initial during assertion of reset , the value of pinit is written into the pll enable (pen) bit of the pll control register, determining whether the pll is enabled or disabled. extal input input external clock/crystal input extal interfaces the internal crystal oscillator input to an external crystal or an external clock. table 3-3. grounds ground name description
signal groupings motorola signal/connection descriptions 3-5 3.1.4 interrupt and mode control table 3-5. interrupt and mode control signal name type state during reset signal description moda irqa input input input (moda) mode select a this input signal has three functions: ? to work with the modb and modc signals to select the dsps initial operating mode, ? to allow an external device to request a dsp interrupt after internal synchronization, and ? to turn on the internal clock generator when the dsp is in the stop processing state, causing the dsp to resume processing. moda is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the moda signal changes to the external interrupt request irqa . the dsp operating mode can be changed by software after reset. external interrupt request a (irqa ) the irqa input is a synchronized external interrupt request. it may be programmed to be level-sensitive or negative-edge triggered. when the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqa will generate multiple interrupts also increases. while the dsp is in the stop mode, asserting irqa gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. hardware reset causes this input to function as moda. modb irqb input input input (modb) mode select b this input signal has two functions: ? to work with the moda and modc signals to select the dsps initial operating mode ? to allow an external device to request a dsp interrupt after internal synchronization modb is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the modb signal changes to the external interrupt request irqb . the dsp operating mode can be changed by software after reset. external interrupt request b (irqb ) the irqb input is a synchronized external interrupt request. it may be programmed to be level-sensitive or negative-edge triggered. when the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on irqb will generate multiple interrupts also increases. hardware reset causes this input to function as modb.
3-6 dsp56012 data sheet motorola signal groupings modc nmi input, edge- triggered input, edge- triggered input (modc) mode select c this input signal has two functions: ? to work with the moda and modb signals to select the dsps initial operating mode ? to allow an external device to request a dsp interrupt after internal synchronization modc is read and internally latched in the dsp when the processor exits the reset state. the logic state present on the moda, modb, and modc pins selects the initial dsp operating mode. several clock cycles after leaving the reset state, the modc signal changes to the non-maskable interrupt request, nmi . the dsp operating mode can be changed by software after reset. non-maskable interrupt request the nmi input is a negative- edge triggered external interrupt request. this is a level 3 interrupt that cannot be masked out. triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. however, as the fall time of the interrupt signal increases, the probability that noise on nmi will generate multiple interrupts also increases. hardware reset causes this input to function as modc. reset input active reset this input causes a direct hardware reset of the processor. when reset is asserted, the dsp is initialized and placed in the reset state. a schmitt-trigger input is used for noise immunity. when the reset signal is deasserted, the initial dsp operating mode is latched from the moda, modb, and modc signals. the dsp also samples the pinit signal and writes its status into the pen bit of the pll control register. when the dsp comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the reset signal. however, the probability that noise on reset will generate multiple resets increases with increasing rise time of the reset signal. for proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware reset state. table 3-5. interrupt and mode control (continued) signal name type state during reset signal description
signal groupings motorola signal/connection descriptions 3-7 3.1.5 host interface (hi) the hi provides a fast parallel data to 8-bit port, which may be connected directly to the host bus. the hi supports a variety of standard buses, and can be directly connected to a number of industry standard microcomputers, microprocessors, dsps, and dma hardware. table 3-6. host interface signal name type state during reset signal description h0Ch7 pb0Cpb7 input/ output input host data bus (h0Ch7) this data bus transfers data between the host processor and the dsp56012. when configured as a host interface port, the h0Ch7 signals are tri-stated as long as hen is deasserted. the signals are inputs unless hr/w is high and hen is asserted, in which case h0Ch7 become outputs, allowing the host processor to read the dsp56012 data. h0Ch7 become outputs when hack is asserted during horeq assertion. port b gpio 0C7 (pb0Cpb7) these signals are gpio (pb0C pb7) when the host interface is not selected. after reset, the default state for these signals is gpio input. hoa0Choa2 pb8Cpb10 input input/ output input host address0Chost address 2 (hoa0Choa2) these inputs provide the address selection for each host interface register. port b gpio 8C10 (pb8Cpb10) these signals are gpio signals (pb8Cpb10) when the host interface is not selected. after reset, the default state for these signals is gpio input. hr/w pb11 input input/ output input host read/write this input selects the direction of data transfer for each host processor access. if hr/w is high and hen is asserted, h0Ch7 are outputs and dsp data is transferred to the host processor. if hr/w is low and hen is asserted, h0C h7 are inputs and host data is transferred to the dsp. hr/w must be stable when hen is asserted. port b gpio 11 (pb11) this signal is a gpio signal (pb11) when the host interface is not being used. after reset, the default state for this signal is gpio input.
3-8 dsp56012 data sheet motorola signal groupings hen pb12 input input/ output input host enable this input enables a data transfer on the host data bus. when hen is asserted and hr/w is high, h0Ch7 become outputs and the host processor may read mc68183 data. when hen is asserted and hr/w is low, h0Ch7 become inputs. host data is latched inside the dsp on the rising edge of hen . normally, a chip select signal derived from host address decoding and an enable strobe are used to generate hen . port b gpio 12 (pb12) this signal is a gpio signal (pb12) when the host interface is not being used. after reset, the default state for this signal is gpio input. horeq pb13 open- drain output input/ output input host request this signal is used by the host interface to request service from the host processor, dma controller, or a simple external controller. note: horeq should always be pulled high when it is not in use. port b gpio 13 (pb13) this signal is a gpio (not open-drain) signal (pb13) when the host interface is not selected. after reset, the default state for this signal is gpio input. hack pb14 input input/ output input host acknowledge this input has two functions. it provides a host acknowledge handshake signal for dma transfers and it receives a host interrupt acknowledge compatible with mc68000 family processors. note: hack should always be pulled high when it is not in use. port b gpio 14 (pb14) this signal is a gpio signal (pb14) when the host interface is not selected. after reset, the default state for this signal is gpio input. table 3-6. host interface (continued) signal name type state during reset signal description
signal groupings motorola signal/connection descriptions 3-9 3.1.6 serial host interface (shi) the shi has five i/o signals that may be configured to allow the shi to operate in either spi or i 2 c mode. table 3-7. serial host interface (shi) signals signal name signal type state during reset signal description sck scl input or output input or output tri-stated spi serial clock the sck signal is an output when the spi is configured as a master, and a schmitt-trigger input when the spi is configured as a slave. when the spi is configured as a master, the sck signal is derived from the internal shi clock generator. when the spi is configured as a slave, the sck signal is an input, and the clock signal from the external master synchronizes the data transfer. the sck signal is ignored by the spi if it is defined as a slave and the slave select (ss ) signal is not asserted. in both the master and slave spi devices, data is shifted on one edge of the sck signal and is sampled on the opposite edge where data is stable. edge polarity is determined by the spi transfer protocol. the maximum allowed internally generated bit clock frequency is f osc /4 for the spi mode, where f osc is the clock on extal. the maximum allowed externally generated bit clock frequency is f osc /3 for the spi mode. i 2 c serial clock scl carries the clock for i 2 c bus transactions in the i 2 c mode. scl is a schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. scl should be connected to v cc through a pull-up resistor. the maximum allowed internally generated bit clock frequency is f osc /6 for the i 2 c mode where f osc is the clock on extal. the maximum allowed externally generated bit clock frequency is f osc /5 for the i 2 c mode. an external pull-up resistor is not required. miso sda input or output input or open-drain output tri-stated spi master-in-slave-out when the spi is configured as a master, miso is the master data input line. the miso signal is used in conjunction with the mosi signal for transmitting and receiving serial data. this signal is a schmitt-trigger input when configured for the spi master mode, an output when configured for the spi slave mode, and tri-stated if configured for the spi slave mode when ss is deasserted. an external pull-up resistor is not required for spi operation. i 2 c data and acknowledge in i 2 c mode, sda is a schmitt-trigger input when receiving and an open-drain output when transmitting. sda should be connected to v cc through a pull-up resistor. sda carries the data for i 2 c transactions. the data in sda must be stable during the high period of scl. the data in sda is only allowed to change when scl is low. when the bus is free, sda is high. the sda line is only allowed to change during the time scl is high in the case of start and stop events. a high to low transition of the sda line while scl is high is a unique situation, which is defined as the start event. a low to high transition of sda while scl is high is an unique situation, which is defined as the stop event.
3-10 dsp56012 data sheet motorola signal groupings mosi ha0 input or output input tri-stated spi master-out-slave-in when the spi is configured as a master, mosi is the master data output line. the mosi signal is used in conjunction with the miso signal for transmitting and receiving serial data. mosi is the slave data input line when the spi is configured as a slave. this signal is a schmitt-trigger input when configured for the spi slave mode. i 2 c slave address 0 this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for i 2 c slave mode, the ha0 signal is used to form the slave device address. ha0 is ignored when it is configured for the i 2 c master mode. an external pull-up resistor is not required. ss ha2 input input tri-stated spi slave select this signal is an active low schmitt-trigger input when configured for the spi mode. when configured for the spi slave mode, this signal is used to enable the spi slave for transfer. when configured for the spi master mode, this signal should be kept deasserted (pulled high). if it is asserted while configured as spi master, a bus error condition is flagged. i 2 c slave address 2 this signal uses a schmitt-trigger input when configured for the i 2 c mode. when configured for the i 2 c slave mode, the ha2 signal is used to form the slave device address. ha2 is ignored in the i 2 c master mode. if ss is deasserted, the shi ignores sck clocks and keeps the miso output signal in the high-impedance state. this signal is tri-stated during hardware, software, or individual reset (thus, there is no need for an external pull-up in this state). hreq input or output tri-stated host request this signal is an active low schmitt-trigger input when configured for the master mode, but an active low output when configured for the slave mode. when configured for the slave mode, hreq is asserted to indicate that the shi is ready for the next data word transfer. it is deasserted at the first clock pulse of the new data word transfer. when configured for the master mode, hreq is an input. when asserted by the external slave device, it will trigger the start of the data word transfer by the master. after finishing the data word transfer, the master will await the next assertion of hreq to proceed to the next transfer. this signal is tri-stated during hardware, software, personal reset, or when the hreq1Chreq0 bits in the hcsr are cleared (no need for external pull-up in this state). table 3-7. serial host interface (shi) signals (continued) signal name signal type state during reset signal description
signal groupings motorola signal/connection descriptions 3-11 3.1.7 serial audio interface (sai) the sai is composed of separate receiver and transmitter sections. 3.1.7.1 sai receive section the receive section of the sai has four dedicated signals . table 3-8. serial audio interface (sai) receive signals signal name signal type state during reset signal description sdi0 input tri-stated serial data input 0 this is the receiver 0 serial data input. this signal is high impedance during hardware or software reset, while receiver 0 is disabled (r0en = 0) or while the chip is in the stop state. no external pull-up resistor is required. sdi1 input tri-stated serial data input 1 this is the receiver 1 serial data input. this signal is high impedance during hardware or software reset, while receiver 1 is disabled (r1en = 0) or while the chip is in the stop state. no external pull-up resistor is required. sckr input or output tri-stated receive serial clock sckr is an output if the receiver section is programmed as a master and a schmitt-trigger input if programmed as a slave. sckr is high impedance if all receivers are disabled (personal reset) and during hardware or software reset or while the chip is in the stop state. no external pull-up is necessary. wsr input or output tri-stated receive word select wsr is an output if the receiver section is programmed as a master and a schmitt-trigger input if programmed as a slave. wsr is used to synchronize the data word and to select the left/right portion of the data sample. wsr is high impedance if all receivers are disabled (personal reset), during hardware reset, during software reset, or while the chip is in the stop state. no external pull-up is necessary.
3-12 dsp56012 data sheet motorola signal groupings 3.1.7.2 sai transmit section the transmit section of the sai has five dedicated signals. table 3-9. serial audio interface (sai) transmit signals signal name signal type state during reset signal description sdo0 output driven high serial data output 0 sdo0 is the transmitter 0 serial output. sdo0 is driven high if transmitter 0 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the stop state. sdo1 output driven high serial data output 1 sdo1 is the transmitter 1 serial output. sdo1 is driven high if transmitter 1 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the stop state. sdo2 output driven high serial data output 2 sdo2 is the transmitter 2 serial output. sdo2 is driven high if transmitter 2 is disabled, during personal reset, hardware reset and software reset, or when the chip is in the stop state. sckt input or output tri-stated transmit serial clock this signal provides the clock for the serial audio interface (sai). the sckt signal can be an output if the transmit section is programmed as a master or a schmitt-trigger input if the transmit section is programmed as a slave. when the sckt is an output, it provides an internally generated sai transmit clock to external circuitry. when the sckt is an input, it allows external circuitry to clock data out of the sai. sckt is tri-stated if all transmitters are disabled (personal reset), during hardware reset, software reset, or while the chip is in the stop state. no external pull-up is necessary. wst input or output tri-stated transmit word select wst is an output if the transmit section is programmed as a master and a schmitt-trigger input if programmed as a slave. wst is used to synchronize the data word and select the left/ right portion of the data sample. wst is tri-stated if all transmitters are disabled (personal reset), during hardware or software reset, or while the chip is in the stop state. no external pull-up is necessary.
signal groupings motorola signal/connection descriptions 3-13 3.1.8 general purpose input/output (gpio) 3.1.9 digital audio interface (dax) table 3-10. general purpose i/o (gpio) signals signal name signal type state during reset signal description gpio0C gpio7 input or output (standard or open-drain) disconnected internally general purpose input/output these signals are used for control and handshake functions between the dsp and external circuitry. each gpio signal may be individually programmed to be one of four states: ? not connected ? input ? standard output ? open-drain output table 3-11. digital audio interface (dax) signals signal name type state during reset signal description ado output output, driven high digital audio data output this signal is an audio and non-audio output in the form of aes/ebu, cp340, and iec958 data in a biphase mark format. the signal is driven high when the dax is disabled and during hardware or software reset. aci input tri-stated audio clock input this is the dax clock input. when programmed to use an external clock, this input supplies the dax clock. the external clock frequency must 256, 384, or 512 times the audio sampling frequency (256 x fs, 384 x fs or 512 x fs, respectively). the aci signal is high impedance (tri- stated) only during hardware or software reset. if the dax is not used, connect the aci signal to ground through an external pull-down resistor to ensure a stable logic level at the input.
3-14 dsp56012 data sheet motorola signal groupings 3.1.10 once port table 3-12. on-chip emulation port (once) signals signal name signal type state during reset signal description dsi os0 input output low output debug serial input in debug mode, serial data or commands are provided as inputs to the once controller via the dsi signal. data is latched on the falling edge of the dsck serial clock. data is always shifted into the once serial port most significant bit (msb) first. when switching from output to input, the signal is tri-stated. chip status 0 when the chip is not in debug mode, this signal is an output that works with the os1 signal to provide information about the chip status. note: if the once interface is in use, an external pull-down resistor should be attached to this pin. if the once interface is not in use, the resistor is not required. dsck os1 input output low output debug serial clock the dsck signal is used in debug mode and supplies the serial input clock to the once module to shift data into and out of the once serial port. (data is clocked into the once port on the falling edge and is clocked out of the once serial port on the rising edge.) the debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. when switching from input to output, the signal is tri-stated. chip status 1 when the chip is not in debug mode, this signal is an output that works with the os0 signal to provide information about the chip status. note: if the once interface is in use, an external pull-down resistor should be attached to this pin. if the once interface is not in use, the resistor is not required. dso output pulled high debug serial output data contained in one of the once controller registers is provided through the dso output signal, as specified by the last command received from the external command controller. data is always shifted out of the once serial port msb first. data is clocked out of the once serial port on the rising edge of dsck. the dso signal also provides acknowledge pulses to the external command controller. when the chip enters the debug mode, the dso signal will be pulsed low to indicate (acknowledge) that the once is waiting for commands. after the once receives a read command, the dso signal is pulsed low to indicate that the requested data is available and the once serial port is ready to receive clocks in order to deliver the data. after the once receives a write command, the dso signal is pulsed low to indicate that the once serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse is provided.
signal groupings motorola signal/connection descriptions 3-15 dr input input debug request a debug request (dr ) input from an external command controller allows the user to enter the debug mode of operation. when dr is asserted, it causes the dsp to finish the current instruction being executed, save the instruction pipeline information, enter the de;bug mode, and wait for commands to be entered from the dsi line. while in debug mode, the dr signal lets the user reset the once controller by asserting it and deasserting it after receiving an acknowledge signal. note: it may be necessary to reset the once controller in cases where synchronization between the once controller and external circuitry is lost. dr must be deasserted after the once responds with an acknowledge on the dso signal and before sending the first once command. asserting dr causes the chip to exit the stop or wait state. having dr asserted during the deassertion of reset causes the dsp to enter debug mode. note: if the once interface is not in use, attach an external pull-up resistor to the dr input. table 3-12. on-chip emulation port (once) signals (continued) signal name signal type state during reset signal description
3-16 dsp56012 data sheet motorola signal groupings
maximum ratings motorola specifications 4-1 part 4 specifications 4.1 introduction the dsp56012 is fabricated in high density cmos with transistor-transistor logic (ttl) compatible inputs and outputs. the dsp56012 specifications are preliminary and are from design simulations. they may not be fully tested or guaranteed at this early stage of the product life cycle. for design convenience, timings for 81 mhz and 95 mhz operation are included. finalized specifications will be published after full characterization and device qualifications are complete. 4.2 maximum ratings warning: this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). note: in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a maximum value for a specification will never occur in the same device that has a minimum value for another specification; adding a maximum to a minimum represents a condition that can never exist. table 4-1. maximum ratings rating 1 symbol value 1, 2 unit supply voltage v cc - 0.3 to +7.0 v all input voltages v in gnd - 0.5 to v cc + 0.5 v current drain per pin excluding v cc and gnd i 10 ma operating temperature range t j C0 to +90 ? c storage temperature t stg - 55 to +125 ? c 1. gnd = 0 v, v cc = 5.0 v 5%, t j = C 0 c to +90 c, cl = 50 pf + 2 ttl loads 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or cause permanent damage to the device.
4-2 dsp56012 data sheet motorola thermal characteristics 4.3 thermal characteristics 4.4 dc electrical characteristics table 4-2. thermal characteristics characteristic symbol tqfp value unit junction-to-ambient thermal resistance 1 r q ja or q ja 47 ? c/w junction-to-case thermal resistance 2 r q jc or q jc 5.8 ? c/w thermal characterization parameter y jt 1.6 ? c/w 1. junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided printed circuit board per semi g38-87 in natural convection.(semi is semiconductor equipment and materials international, 805 east middlefield rd., mountain view, ca 94043, (415) 964-5111) measurements were done with parts mounted on thermal test boards conforming to specification eia/jesd51-3. 2. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88, with the exception that the cold plate temperature is used for the case temperature. table 4-3. dc electrical characteristics characteristics symbol min typ max unit supply voltage v cc 4.75 5.0 5.25 v input high voltage ? extal ? reset ? moda, modb, modc ? aci, shi inputs1 ? all other inputs v ihc v ihr v ihm v ihs v ih 4.0 2.5 3.5 0.7 v cc 2.0 v cc v cc v cc v cc v cc v v v v v input low voltage ? extal ? moda, modb, modc ? aci, shi inputs 1 ? all other inputs v ilc v ilm v ils v il C0.5 C0.5 C0.5 C0.5 0.6 2.0 0.3 v cc 0.8 v v v v input leakage current ? extal, reset , moda, modb, modc, dr ? other input pins (@ 2.4 v/0.4 v) i in C1 C10 1 10 m a m a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi C10 10 m a output high voltage (i oh = C0.4 ma) v oh 2.4 v output low voltage (i ol = 3.2 ma) sck/scl i ol = 6.7 ma miso/sda i ol = 6.7 ma horeq i ol = 6.7 ma v ol 0.4 v internal supply current @ 95 mhz ? normal mode 2 ? wait mode ? stop mode 3 i cci i ccw i ccs 140 22 1.5 150 30 5 ma ma ma
internal clocks motorola specifications 4-3 4.5 ac electrical characteristics the timing waveforms in the ac electrical characteristics are tested with a v il maximum of 0.5 v and a v ih minimum of 2.4 v for all inputs, except extal, reset , moda, modb, modc, aci, and shi inputs (mosi/ha0, ss /ha2, miso/sda, sck/scl, hreq ). these inputs are tested using the input levels set forth in the dc electrical characteristics. ac timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signals transition. dsp56012 output levels are measured with the production test machine v ol and v oh reference levels set at 0.8 v and 2.0 v, respectively. all output delays are given for a 50 pf load unless otherwise specified. for load capacitance greater than 50 pf, the drive capability of the output pins typically decreases linearly: 1. at 1.5 ns per 10 pf of additional capacitance at all output pins except mosi/ha0, miso/sda, sck/scl, hreq 2. at 1.0 ns per 10 pf of additional capacitance at output pins mosi/ha0, miso/sda, sck/scl, hreq (in spi mode only) 4.6 internal clocks pll supply current @ 95 mhz 1.2 2.0 ma input capacitance 4 c in 10 pf 1. the shi inputs are mosi/ha0, ss /ha2, miso/sda, sck/scl, and hreq . 2. maximum values can be derived using the methodology described in section 6, design considerations, on page 6-1. actual maximums are application dependent and may vary widely. 3. in order to obtain these results, all inputs must be terminated (i.e., not allowed to float). pll signals are disabled during stop state. 4. periodically sampled and not 100% tested table 4-4. internal clocks characteristics symbol expression minimum maximum internal operation frequency f 0 95 mhz internal clock high period ? with pll disabled (see note) ? with pll enabled and mf 4 ? with pll enabled and mf > 4 t h et hminimum 0.48 t c 0.467 t c et hmaximum 0.52 t c 0.533 t c internal clock low period ? with pll disabled (see note) ? with pll enabled and mf 4 ? with pll enabled and mf > 4 t l et lminimum 0.48 t c 0.467 t c et lmaximum 0.52 t c 0.533 t c internal clock cycle time t c (df et c )/mf instruction cycle time i cyc 2 t c note: see table 4-5. for external clock (et) specifications. table 4-3. dc electrical characteristics (continued) characteristics symbol min typ max unit
4-4 dsp56012 data sheet motorola external clock operation 4.7 external clock operation the dsp56012 system clock is externally supplied via the extal pin. timings shown in this document are valid for clock rise and fall times of 3 ns maximum. the 81 mhz speed allows the dsp56012 to take advantage of the 27 mhz system clock in dvd applications. table 4-5. external clock (extal) no. characteristics sym. 81 mhz 95 mhz unit min max min max frequency of external clock extal e f 081095mhz 1 external clock input highextal ? with pll disabled (46.7%C53.3% duty cycle) ? with pll enabled (42.5%C57.5% duty cycle) et h 5.8 5.2 235500 4.9 4.5 235500 ns ns 2 external clock input lowextal ? with pll disabled (46.7%C53.3% duty cycle) ? with pll enabled (42.5%C57.5% duty cycle) et l 5.8 5.2 235500 4.9 4.5 235500 ns ns 3 external clock cycle time ? with pll disabled ? with pll enabled et c 12.3 12.3 409600 10.5 10.5 409600 ns ns 4 instruction cycle time = i cyc = 2 t c with pll disabled with pll enabled i cyc 24.7 24.7 819200 21.0 21.0 819200 ns ns note: extal input high and input low are measured at 50% of the input transition. figure 4-1. external clock timing et h et l et c extal 1 2 3 4 aa0250
reset, stop, mode select, and interrupt timing motorola specifications 4-5 4.8 phase-locked loop (pll) characteristics 4.9 reset, stop, mode select, and interrupt timing table 4-6. phase-locked loop (pll) characteristics characteristics expression min max unit vco frequency when pll enabled mf e f 10 f mhz pll external capacitor (pcap pin to v ccp ) mf c pcap @ mf 4 @ mf > 4 mf 340 mf 380 mf 480 mf 970 pf pf note: cpcap is the value of the pll capacitor (connected between pcap pin and v ccp ) for mf = 1. the recommended value for cpcap is 400 pf for mf 4 and 540 pf for mf > 4. the maximum vco frequency is limited to the internal operation frequency defined in table 4-4. on page -3. table 4-7. reset, stop, mode select, and interrupt timing no. characteristics all frequencies unit min max 10 minimum reset assertion width: ? pll disabled ? pll enabled 1 25 t c 2500 et c ns ns 14 mode select setup time 21 ns 15 mode select hold time 0 ns 16 minimum edge-triggered interrupt request assertion width 13 ns 16a minimum edge-triggered interrupt request deassertation width 13 ns 18 delay from irqa , irqb , nmi assertion to gpio valid caused by first interrupt instruction execution ? gpio0Cgpio7 ? pb0Cpb14 12 t c + t h 11 t c + t h ns ns 22 delay from general purpose output valid to interrupt request deassertion for level sensitive fast interrupts if second interrupt instruction is: 2 ? single cycle ? two cycles t l C 31 (2 t c ) + t l C 31 ns ns 25 duration of irqa assertion for recovery from stop state 12 ns 27 duration for level-sensitive irqa assertion to ensure interrupt service (when exiting stop mode) ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17 = 1 6 t c + t l 12 ns ns
4-6 dsp56012 data sheet motorola reset, stop, mode select, and interrupt timing 1. this timing requirement is sensitive to the quality of the external pll capacitor connected to the pcap pin. for capacitor values less than or equal to 2 nf, asserting reset according to this timing requirement will ensure proper processor initialization for capacitors with a delta c/c less than 0.5%. (this is typical for ceramic capacitors.) for capacitor values greater than 2 nf, asserting reset according to this timing requirement will ensure proper processor initialization for capacitors with a delta c/c less than 0.01%. (this is typical for teflon, polystyrene, and polypropylene capacitors.) however, capacitors with values greater than 2 nf with a delta c/ c greater than 0.01% may require longer reset assertion to ensure proper initialization. 2. when using fast interrupts with irqa and irqb defined as level-sensitive, timing 22 applies to prevent multiple interrupt service. to avoid these timing restrictions, negative-edge-triggered configuration is recommended when using fast interrupts. long interrupts are recommended when using level-sensitive configuration. figure 4-2. reset timing figure 4-3. operating mode select timing figure 4-4. external interrupt timing (negative-edge triggered) table 4-7. reset, stop, mode select, and interrupt timing (continued) no. characteristics all frequencies unit min max reset 10 v ihr aa0251 v ihm v ilm v ih v il reset moda, modb modc v ihr irqa , irqb , nmi 14 15 aa0252 irqa , irqb , nmi 16 16a irqa , irqb , nmi aa0253
host interface (hi) timing motorola specifications 4-7 4.10 host interface (hi) timing note: active low lines should be pulled up in a manner consistent with the ac and dc specifications. figure 4-5. external level-sensitive fast interrupt timing figure 4-6. recovery from stop state using irqa figure 4-7. recovery from stop state using irqa interrupt service table 4-8. host i/o timing (all frequencies) num characteristics min max unit 31 hen /hack assertion width 1 ? cvr, icr, isr, rxl read ? ivr, rxh/m read ? write t c + 31 26 13 ns 32 hen /hack deassertion width 1 ? after txl writes 2 ? after rxl reads 3 ? between two cvr, icr, or isr reads 13 2 t c + 31 2 t c + 31 2 t c + 31 ns ns ns ns 33 host data input setup time before hen /hack deassertion 4 ns general purpose i/o general purpose i/o (output) irqa irqb nmi 22 18 aa0254 irqa 25 aa0255 irqa 27 aa0256
4-8 dsp56012 data sheet motorola host interface (hi) timing 34 host data input hold time after hen /hack deassertion 3 ns 35 hen /hack assertion to output data active from high impedance 0ns 36 hen /hack assertion to output data valid 26 ns 37 hen /hack deassertion to output data high impedance 4 18ns 38 output data hold time after hen /hack deassertion 5 2.5 ns 39 hr/w low setup time before hen assertion 0 ns 40 hr/w low hold time after hen deassertion 3 ns 41 hr/w high setup time to hen assertion 0 ns 42 hr/w high hold time after hen /hack deassertion 3 ns 43 hoa0Choa2 setup time before hen assertion 0 ns 44 hoa0Choa2 hold time after hen deassertion 3 ns 45 dma hack assertion to horeq deassertion 6 345ns 46 dma hack deassertion to horeq assertion 4,6 ? for dma rxl read ? for dma txl write ? all other cases t l + t c + t h t l + t c 0 ns ns ns 47 delay from hen deassertion to horeq assertion for rxl read 4,6 t l + t c + t h ns 48 delay from hen deassertion to horeq assertion for txl write 4,6 t l + t c ns 49 delay from hen assertion to horeq deassertion for rxl read, txl write 4,6 358ns 1. see section 6.5, host port considerations, on page 6-5. 2. this timing is applicable only if a write to the txl is followed by writing the txl, txm, or txh registers without first polling the txde or horeq flags, or waiting for horeq to be asserted. 3. this timing is applicable only if a read from the rxl is followed by reading the rxl, rxm or rxh registers without first polling the rxdf or horeq flags, or waiting for horeq to be asserted. 4. specifications are periodically sampled and not 100% tested. 5. may decrease to 0 ns for future versions 6. horeq is pulled up by a 1 k w resistor. table 4-8. host i/o timing (all frequencies) (continued) num characteristics min max unit
host interface (hi) timing motorola specifications 4-9 figure 4-8. host interrupt vector register (ivr) read figure 4-9. host read cycle (non-dma mode) horeq (output) hack (input) hr/w (input) h0Ch7 (output) 31 35 32 42 41 37 38 36 data valid aa1275 horeq (output) hen (input) ha2Cha0 (input) hr/w (input) h0Ch7 (output) 31 43 data valid address valid 32 44 41 address valid address valid 36 38 37 49 47 35 data valid data valid 42 rxh read rxm read rxl read aa1276
4-10 dsp56012 data sheet motorola host interface (hi) timing figure 4-10. host write cycle (non-dma mode) figure 4-11. host dma read cycle horeq (output) hen (input) ha2Cha0 (input) hr/w (input) h0Ch7 (output) 31 43 aa1277 data valid address valid 32 44 39 address valid address valid 34 49 48 33 40 txh write txm write txl write data valid data valid horeq (output) hack (input) h0Ch7 (output) 45 35 aa1278 data valid 46 data valid data valid 37 rxh read rxm read rxl read 31 46 46 32 36 38
host interface (hi) timing motorola specifications 4-11 figure 4-12. host dma write cycle horeq (output) hack (input) h0Ch7 (output) 45 aa1279 46 txh write txm write txl write 31 46 46 32 33 34 data valid data valid data valid
4-12 dsp56012 data sheet motorola serial audio interface (sai) timing) 4.11 serial audio interface (sai) timing) table 4-9. serial audio interface (sai) timing no. characteristics mode expression 81 mhz 95 mhz unit min max min max 111 minimum serial clock cycle = t saicc (min) master 4 t c 49.4 42 ns slave 3 t c + 5 42 36.5 ns 112 serial clock high period master 0.5 t saicc C 8 16.7 13 ns slave 0.35 t saicc 14.7 12.8 ns 113 serial clock low period master 0.5 t saicc C 8 16.7 13 ns slave 0.35 t saicc 14.7 12.8 ns 114 serial clock rise/fall time master 8 88ns slave 0.15 t saicc 6.3 5.5 ns 115 data input valid to sckr edge (data input setup time) master 26 26 26 ns slave 4 44ns 116 sckr edge to data input not valid (data input hold time) master 0 00ns slave 14 14 14 ns 117 sckr edge to word select output valid (wsr out delay time) master 20 20 20 ns 118 word select input valid to sckr edge (wsr in setup time) slave 12 12 12 ns 119 sckr edge to word select input not valid (wsr in hold time) slave 12 12 12 ns 121 sckt edge to data output valid (data out delay time) master 13 13 13 ns slave 1 40 4040ns slave 2 t h + 34 40.2 39.25 ns 122 sckt edge to word select output valid (wst output delay time) master 19 19 19 ns 123 word select input valid to sckt edge (wst in setup time) slave 12 12 12 ns 124 sckt edge to word select input not valid (wst in hold time) slave 12 12 12 ns 1. when the frequency ratio between parallel and serial clocks is 1:4 or greater 2. when the frequency ratio between parallel and serial clocks is 1:3C1:4
serial audio interface (sai) timing) motorola specifications 4-13 figure 4-13. sai receiver timing sckr (rckp = 1) sckr (rckp = 0) valid valid wsr (output) wsr (input) sdi0Csdi1 (data input) 111 112 113 111 113 114 114 112 116 115 118 119 117 114 114 aa0269
4-14 dsp56012 data sheet motorola serial audio interface (sai) timing) figure 4-14. sai transmitter timing valid 111 112 113 111 113 114 114 112 121 123 124 122 aa0270 114 114 sckt (tckp = 1) sckt (tckp = 0) wst (output) wst (input) sdo0Csdo2) (data output)
serial host interface (shi) spi protocol timing motorola specifications 4-15 4.12 serial host interface (shi) spi protocol timing table 4-10. serial host interface (shi) spi protocol timing no. characteristics mode filter mode expression 81 mhz 95 mhz unit min max min max tolerable spike width on clock or data input bypassed narrow wide 0 20 100 0 20 100 ns ns ns 141 minimum serial clock cycle = t spicc (min) ? frequency below 33 mhz 1 master bypassed 4 t c ns ? frequency above 33 mhz 1 master bypassed 6 t c 74.1 63 ns narrow 1000 1000 1000 ns wide 2000 2000 2000 ns cpha = 0, cpha = 1 2 slave bypassed 3 t c 37 31.5 ns narrow 3 t c + 25 62 56.5 ns wide 3 t c + 85 122 116.5 ns cpha = 1 slave bypassed 3 t c + 79 116 110.5 ns narrow 3 t c + 431 468 462.5 ns wide 3 t c + 1022 1059 1053. 5 ns 142 serial clock high period master 0.5 t spicc C10 27.0 21.5 ns cpha = 0, cpha = 1 2 slave bypassed t c + 8 20.3 18.5 ns narrow t c + 31 43.3 41.5 ns wide t c + 43 55.3 53.5 ns cpha = 1 slave bypassed t c + t h + 40 58.5 55.75 ns narrow t c + t h + 216 235 231.7 5 ns wide t c + t h + 511 536 526.7 5 ns 143 serial clock low period master 0.5 t spicc C10 27.0 21.5 ns cpha = 0, cpha = 1 2 slave bypassed t c + 8 20.3 18.5 ns narrow t c + 31 43.3 41.5 ns wide t c + 43 55.3 53.5 ns cpha = 1 slave bypassed t c + t h + 40 58.5 55.75 ns narrow t c + t h + 216 235 231.7 5 ns wide t c + t h + 511 536 526.7 5 ns 144 serial clock rise/fall time master 10 10 10 ns slave 2000 2000 2000 ns
4-16 dsp56012 data sheet motorola serial host interface (shi) spi protocol timing 146 ss assertion to first sck edge cpha = 0 slave bypassed t c + t h + 35 53.5 50.75 ns narrow t c + t h + 35 53.5 50.75 ns wide t c + t h + 35 53.5 50.75 ns cpha = 1 slave bypassed 6 66ns narrow 0 00ns wide 0 00ns 147 last sck edge to ss not asserted cpha = 0 slave bypassed t c + 6 18.3 16.5 ns narrow t c + 70 82.4 80.5 ns wide t c + 197 209 207.5 ns cpha = 1 3 slave bypassed 2 22ns narrow 66 66 66 ns wide 193 193 193 ns 148 data input valid to sck edge (data input setup time) master bypassed 0 00ns narrow max {(37 Ct c ), 0} 25 26.5 ns wide max {(52 Ct c ), 0} 40 41.5 ns slave bypassed 0 00ns narrow max {(38 Ct c ), 0} 26 27.5 ns wide max {(53 Ct c ), 0} 41 42.5 ns 149 sck edge to data input not valid (data in hold time) master bypassed 2 t c + 17 41.7 38 ns narrow 2 t c + 18 42.7 39 ns wide 2 t c + 28 52.7 49 ns slave bypassed 2 t c + 17 41.7 38 ns narrow 2 t c + 18 42.7 39 ns wide 2 t c + 28 52.7 49 ns 150 ss assertion to data out active slave 4 44ns 151 ss deassertion to data tri- stated 4 slave 24 24 24 ns table 4-10. serial host interface (shi) spi protocol timing (continued) no. characteristics mode filter mode expression 81 mhz 95 mhz unit min max min max
serial host interface (shi) spi protocol timing motorola specifications 4-17 152 sck edge to data out valid (data out delay time) master bypassed 41 41 41 ns narrow 214 214 214 ns wide 504 504 504 ns cpha = 0, cpha = 1 2 slave bypassed 41 41 41 ns narrow 214 214 214 ns wide 504 504 504 ns cpha = 1 slave bypassed t c + t h + 40 58.5 55.75 ns narrow t c + t h + 216 235 231.7 5 ns wide t c + t h + 511 536 536 ns 153 sck edge to data out not valid (data out hold time) master bypassed 0 00ns narrow 57 57 57 ns wide 163 163 163 ns slave bypassed 0 00ns narrow 57 57 57 ns wide 163 163 163 ns 154 ss assertion to data output valid cpha = 0 slave t c + t h + 35 53.5 50.75 ns 157 first sck sampling edge to hreq output deassertation slave bypassed 3 t c + t h + 32 75 68.75 ns narrow 3 t c + t h + 209 252 245.7 5 ns wide 3 t c + t h + 507 550 543.7 5 ns 158 last sck sampling edge to hreq output not deasserted cpha = 1 slave bypassed 2 t c + t h + 6 36.9 32.25 ns narrow 2 t c + t h + 63 93.9 89.25 ns wide 2 t c + t h + 169 200 195.2 5 ns 159 ss deassertion to hreq output not deasserted cpha = 0 slave 2 t c + t h + 7 37.9 33.25 ns 160 ss deassertion pulse width cpha = 0 slave t c + 4 16.3 14.5 ns 161 hreq input assertion to first sck edge master 0.5 t spicc + 2 t c + 6 67.7 58.5 ns 162 hreq input deassertion to last sck sampling edge (hreq input setup time) cpha = 1 master 0 00ns table 4-10. serial host interface (shi) spi protocol timing (continued) no. characteristics mode filter mode expression 81 mhz 95 mhz unit min max min max
4-18 dsp56012 data sheet motorola serial host interface (shi) spi protocol timing 163 first sck edge to hreq input not asserted (hreq input hold time) master 0 00ns 1. for an internal clock frequency below 33 mhz, the minimum permissible internal clock to sck frequency ratio is 4:1. for an internal clock frequency above 33 mhz, the minimum permissible internal clock to sck frequency ratio is 6:1. 2. in cpha = 1 mode, the spi slave supports data transfers at t spicc = 3 t c , if the user assures that the htx is written at least t c ns before the first edge of sck of each word. in cpha = 1 mode, the spi slave supports data transfers at t spicc = 3 t c , if the user assures that the htx is written at least t c ns before the first edge of sck of each word. 3. when cpha = 1, the ss line may remain active low between successive transfers. 4. periodically sampled, not 100% tested figure 4-15. spi master timing (cpha = 0) table 4-10. serial host interface (shi) spi protocol timing (continued) no. characteristics mode filter mode expression 81 mhz 95 mhz unit min max min max ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 149 149 148 152 153 163 161 aa0271
serial host interface (shi) spi protocol timing motorola specifications 4-19 figure 4-16. spi master timing (cpha = 1) ss (input) sck (cpol = 0) (output) sck (cpol = 1) (output) miso (input) valid mosi (output) msb valid lsb msb lsb hreq (input) 141 142 143 144 144 141 144 144 143 142 148 148 149 152 153 163 161 162 149 aa0272
4-20 dsp56012 data sheet motorola serial host interface (shi) spi protocol timing figure 4-17. spi slave timing (cpha = 0) ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 141 144 144 143 142 154 150 152 153 148 149 159 157 153 151 valid valid 148 149 147 160 146 aa0273
serial host interface (shi) i2c protocol timing motorola specifications 4-21 4.13 serial host interface (shi) i 2 c protocol timing r p (min) = 1.5 k w figure 4-18. spi slave timing (cpha = 1) table 4-11. shi i 2 c protocol timing standard i 2 c (c l = 400 pf, r p = 2 k w , 100 khz) no. characteristics symbol all frequencies unit min max tolerable spike width on scl or sda filters bypassed 0 ns narrow filters enabled 20 ns wide filters enabled 100 ns 171 minimum scl serial clock cycle t scl 10.0 m s 172 bus free time t buf 4.7 m s ss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) miso (output) mosi (input) msb lsb msb lsb hreq (output) 141 142 143 144 144 144 144 143 142 150 152 148 149 158 153 151 valid valid 148 147 146 152 149 157 aa0274
4-22 dsp56012 data sheet motorola programming the serial clock 4.14 programming the serial clock the programmed serial clock cycle, t i 2 ccp , is specified by the value of the hdm5Chdm0 and hrs bits of the hckr (shi clock control register). the expression for t i 2 ccp is as follows: t i 2 ccp = [t c 2 (hdm[5:0] + 1) (7 (1 C hrs) + 1)] where hrs is the prescaler rate select bit. when hrs is cleared, the fixed divide-by-eight prescaler is operational. when hrs is set, the prescaler is bypassed. mdm5Chdm0 are the divider modulus select bits. a divide ratio from 1 to 64 (hdm5Chdm0 = 0 to $3f) may be selected. in i 2 c mode, you may select a value for the programmed serial clock cycle from: 6 t c (if hdm[5:0] = $02 and hrs = 1) to 1024 t c (if hdm[5:0] = $3f and hrs = 0) the dsp56012 provides an improved i 2 c bus protocol. in addition to supporting the 100 khz i 2 c bus protocol, the shi in i 2 c mode supports data transfers at up to 1000 khz. the actual maximum frequency is limited by the bus capacitances (c l ), the pull-up resistors (r p ) (which affect the rise and fall time of sda and scl, see table 4-12. on page -23), and by the input filters. 173 start condition setup time t su;sta 4.7 m s 174 start condition hold time t hd;sta 4.0 m s 175 scl low period t low 4.7 m s 176 scl high period t high 4.0 m s 177 scl and sda rise time t r 1.0 m s 178 scl and sda fall time t f 0.3 m s 179 data setup time t su;dat 250 ns 180 data hold time t hd;dat 0.0 ns 182 scl low to data output valid t vd;dat 3.4 m s 183 stop condition setup time t su;sto 4.0 m s table 4-11. shi i 2 c protocol timing standard i 2 c (c l = 400 pf, r p = 2 k w , 100 khz) no. characteristics symbol all frequencies unit min max
programming the serial clock motorola specifications 4-23 4.14.1 considerations for programming the shi clock control register (hckr)clock divide ratio the master must generate a bus free time greater than t172 slave when operating with a dsp56012 shi i 2 c slave. table 4-12. describes a few examples. example: for c l = 50 pf, r p = 2 k w , f = 81 mhz, bypassed filter mode: the master, when operating with a dsp56012 shi i 2 c slave with an 81 mhz operating frequency, must generate a bus free time greater than 36 ns (t172 slave). thus, the minimum permissible t i 2 ccp is 52 t c , which gives a bus free time of at least 41 ns (t172 master). this implies a maximum i 2 c serial frequency of 1010 khz. in general, bus performance may be calculated from the c l and r p of the bus (the input filter modes and operating frequencies of the master and the slave). table 4-13. on page -24 contains the expressions required to calculate all relevant performance timing for a given c l and r p . note: t177 (t r ) is computed using the values of c l and r p, and t178 (t f ) is computed using the value of c l . the two values are used in computing many of the other timing values in table 4-13 on page 4-24. table 4-12. considerations for programming the shi clock control register (hckr) conditions to be considered resulting limitations bus load master oper- ating freq. slave oper- ating freq. master filter mode slave filter mode t172 slave min. per- missible t i 2 ccp t172 master maximum i 2 c serial frequency c l = 50 pf, r p = 2 k w 81 mhz 81 mhz bypassed narrow wide bypassed narrow wide 36 ns 60 ns 95 ns 52 t c 56 t c 62 t c 41 ns 66 ns 103 ns 1010 khz 825 khz 634 khz c l = 50 pf, r p = 2 k w 95 mhz 95 mhz bypassed narrow wide bypassed narrow wide 32 ns 56 ns 91 ns 60 t c 64 t c 71 t c 35 ns 56 ns 92.8 ns 1030 khz 843 khz 645 khz
4-24 dsp56012 data sheet motorola programming the serial clock table 4-13. shi improved i 2 c protocol timing improved i 2 c (c l = 50 pf, r p = 2 k w ) no. characteristic sym. mode filter mode expression 81 mhz 1 95 mhz 2 unit min max min max tolerable spike width on scl or sda bypassed narrow wide 0 20 100 0 20 100 0 20 100 ns ns ns 171 scl serial clock cycle t scl master bypassed t i 2 ccp + 3 t c + 72 +t r 989 971.5 ns narrow t i 2 ccp + 3 t c + 245 + t r 1212 1186. 5 ns wide t i 2 ccp + 3 t c + 535 + t r 1576 1550 ns slave bypassed 4 t c + t h + 172 + t r 466 457.3 ns narrow 4 t c + t h + 366 + t r 660 651.3 ns wide 4 t c + t h + 648 + t r 942 933.3 ns 172 bus free time t buf master bypassed 0.5 t i 2 ccp C 42 C t r 41.1 35 ns narrow 0.5 t i 2 ccp C 42 C t r 65.8 56 ns wide 0.5 t i 2 ccp C 42 C t r 103 92.8 ns slave bypassed 2 t c + 11 35.7 32 ns narrow 2 t c + 35 59.7 56 ns wide 2 t c + 70 94.7 91 ns 173 start condition setup time t su;sta slave bypassed 12 12 12 ns narrow 50 50 50 ns wide 150 150 150 ns 174 start condition hold time t hd;sta master bypassed 0.5 t i 2 ccp + 12 C t f 313 307 ns narrow 0.5 t i 2 ccp + 12 C t f 338 328 ns wide 0.5 t i 2 ccp + 12 C t f 375 364.8 ns slave bypassed 2 t c + t h + 21 51.9 47.25 ns narrow 2 t c + t h + 100 131 126.2 5 ns wide 2 t c + t h + 200 231 226.2 5 ns 175 scl low period t low master bypassed 0.5 t i 2 ccp + 18 C t f 319 313 ns narrow 0.5 t i 2 ccp + 18 C t f 344 334 ns wide 0.5 t i 2 ccp + 18 C t f 381 370.7 5 ns slave bypassed 2 t c + 74 + t r 337 333 ns narrow 2 t c + 286 + t r 548. 6 545 ns wide 2 t c + 586 + t r 849 845 ns
programming the serial clock motorola specifications 4-25 176 scl high period t high master bypassed 0.5 t i 2 ccp +2 t c + 19 365 355 ns narrow 0.5 t i 2 ccp +2 t c + 144 514 501 ns wide 0.5 t i 2 ccp + 2 t c + 356 763 749.8 ns slave bypassed 2 t c + t h C 1 30 25.25 ns narrow 2 t c + t h + 18 49 44.25 ns wide 2 t c + t h + 30 61 56.25 ns 177 scl rise time output t r 1.7 r p (c l + 20) 3 238 238 ns input 2000 2000 2000 ns 178 scl fall time output t f 20 + 0.1 (c l C 50) 3 20 20 ns input 2000 2000 2000 ns 179 data setup time t su;dat bypassed t c + 8 20 18.5 ns narrow t c + 60 72 70.5 ns wide t c + 74 86 84.5 ns 180 data hold time t hd;dat bypassed narrow wide 0 0 0 0 0 0 0 0 0 ns ns ns 182 scl low to data output valid t vd;dat bypassed 2 t c + 71 + t r 334 330 ns narrow 2 t c + 244 + t r 507 503 ns wide 2 t c + 535 + t r 798 794 ns 183 stop condition setup time t su;sto master bypassed 0.5 t i 2 ccp + t c + t h + 11 351 341.7 5 ns narrow 0.5 t i 2 ccp + t c + t h + 69 433 420.7 5 ns wide 0.5 t i 2 ccp + t c + t h + 183 584 571.5 ns slave bypassed 11 11 11 ns narrow 50 50 50 ns wide 150 150 150 ns 184 hreq input deassertion to last scl edge (hreq in setup time) master bypassed 0 0 0 ns narrow 0 0 0 ns wide 0 0 0 ns 186 first scl sampling edge to hreq output deassertation slave bypassed 3 t c + t h + 32 75 68.75 ns narrow 3 t c + t h + 209 252 245.7 5 ns wide 3 t c + t h + 507 550 543.7 ns table 4-13. shi improved i 2 c protocol timing (continued) improved i 2 c (c l = 50 pf, r p = 2 k w ) no. characteristic sym. mode filter mode expression 81 mhz 1 95 mhz 2 unit min max min max
4-26 dsp56012 data sheet motorola programming the serial clock 187 last scl edge to hreq output not deasserted slave bypassed 2 t c + t h + 6 37 32.25 ns narrow 2 t c + t h + 63 93.9 89.25 ns wide 2 t c + t h + 169 200 195.2 5 ns 188 hreq input assertion to first scl edge master bypassed t i 2 ccp + 2 t c + 6 673 657 ns narrow t i 2 ccp + 2 t c + 6 722 699 ns wide t i 2 ccp + 2 t c + 6 796 772.5 ns 189 first scl edge to hreq input not asserted (hreq input hold time) master 0 0 0 ns 1. a t i 2 ccp of 52 t c (the maximum permitted for the given bus load) was used for the calculations in the bypassed filter mode. a t i 2 ccp of 56 t c (the maximum permitted for the given bus load) was used for the calculations in the narrow filter mode. a t i 2 ccp of 62 t c (the maximum permitted for the given bus load) was used for the calculations in the wide filter mode. 2. a t i 2 ccp of 60 t c (the maximum permitted for the given bus load) was used for the calculations in the bypassed filter mode. a t i 2 ccp of 64 t c (the maximum permitted for the given bus load) was used for the calculations in the narrow filter mode. a t i 2 ccp of 71 t c (the maximum permitted for the given bus load) was used for the calculations in the wide filter mode. 3. c l is in pf, r p is in k w , and result is in ns. figure 4-19. i 2 c timing table 4-13. shi improved i 2 c protocol timing (continued) improved i 2 c (c l = 50 pf, r p = 2 k w ) no. characteristic sym. mode filter mode expression 81 mhz 1 95 mhz 2 unit min max min max start scl hreq sda ack msb lsb stop 171 stop 173 176 175 177 178 180 179 172 186 182 183 189 174 188 184 187 aa0275
general purpose input/output (gpio) timing motorola specifications 4-27 4.15 general purpose input/output (gpio) timing table 4-14. gpio timing no. characteristics expression all frequencies unit min max 201 extal edge to gpio output valid (gpio output delay time) 26 26 ns 202 extal edge to gpio output not valid (gpio output hold time) 22ns 203 gpio input valid to extal edge (gpio input setup time) 10 10 ns 204 extal edge to gpio input not valid (gpio input hold time) 66ns figure 4-20. gpio timing valid (input) (output) extal (input) (see note) note: valid when the ratio between extal frequency and internal clock frequency equals 1 201 202 204 203 pb0Cpb14 pb0Cpb14 gpio0Cgpio7 gpio0Cgpio7 aa1284
4-28 dsp56012 data sheet motorola digital audio transmitter (dax) timing 4.16 digital audio transmitter (dax) timing table 4-15. 56012 digital audio transmitter timing no. characteristic all frequencies unit min max aci frequency (see note) 25 mhz 220 aci period 40 ns 221 aci high duration 0.5 t c ns 222 aci low duration 0.5 t c ns 223 aci rising edge to ado valid 35 ns note: in order to assure proper operation of the dax, the aci frequency should be less than 1/2 of the dsp56012 internal clock frequency. for example, if the dsp56012 is running at 40 mhz internally, the aci frequency should be less than 20 mhz. figure 4-21. digital audio transmitter timing aci ado 220 223 aa1280 221 222
on-chip emulation (once) timing motorola specifications 4-29 4.17 on-chip emulation (once) timing table 4-16. once timing no. characteristics all frequencies unit min max 230 dsck low 40 ns 231 dsck high 40 ns 232 dsck cycle time 200 ns 233 dr asserted to dso (ack ) asserted 5 t c ns 234 dsck high to dso valid 42 ns 235 dsck high to dso invalid 3 ns 236 dsi valid to dsck low (setup) 15 ns 237 dsck low to dsi invalid (hold) 3 ns 238 last dsck low to os0Cos1, ack active 3 t c + t l ns 239 dso (ack ) asserted to first dsck high 2 t c ns 240 dso (ack ) assertion width 4 t c + t h C 3 5 t c + 7 ns 241 dso (ack ) asserted to os0Cos1 high impedance 1 0ns 242 os0Cos1 valid to second extal transition t c C 21 ns 243 second extal transition to os0Cos1 invalid 0 ns 244 last dsck low of read register to first dsck high of next command 7 t c + 10 ns 245 last dsck low to dso invalid (hold) 3 ns 246 dr assertion to second extal transition for wake up from wait state 10 t c C 10 ns 247 second extal transition to dso after wake up from wait state 17 t c ns 248 dr assertion width ? to recover from wait ? to recover from wait and enter debug mode 15 13 t c + 15 12 t c C 15 ns 249 dr assertion to dso (ack ) valid (enter debug mode) after asynchronous recovery from wait state 17 t c ns 250a dr assertion width to recover from stop 2 ? stable external clock, omr bit 6 = 0 ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17 = 1 15 15 15 65548 t c + t l 20 t c + t l 13 t c + t l ns 250b dr assertion width to recover from stop and enter debug mode 2 ? stable external clock, omr bit 6 = 0 ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17= 1 65549 t c + t l 21 t c + t l 14 t c + t l ns 251 dr assertion to dso (ack ) valid (enter debug mode) after recovery from stop state 2 ? stable external clock, omr bit 6 = 0 ? stable external clock, omr bit 6 = 1 ? stable external clock, pctl bit 17= 1 65553 t c + t l 25 t c + t l 18 t c + t l ns
4-30 dsp56012 data sheet motorola on-chip emulation (once) timing note: 1. maximum t l 2. periodically sampled, not 100% tested figure 4-22. dsp56012 once serial clock timing figure 4-23. dsp56012 once acknowledge timing figure 4-24. dsp56012 once data i/o to status timing table 4-16. once timing (continued) no. characteristics all frequencies unit min max dsck (input) 246 246 231 232 230 aa0277 dr (input) dso (output) ack 233 240 aa0278 dsck (input) dso (output) (ack ) (os1) dsi (input) (os0) (note 1) note: high impedance, external pull-down resistor (last) 236 237 238 aa0279
on-chip emulation (once) timing motorola specifications 4-31 figure 4-25. dsp56012 once read timing figure 4-26. dsp56012 once data i/o status timing figure 4-27. dsp56012 once extal to status timing dsck (input) dso (output) (os0) (note 1) note: high impedance, external pull-down resistor (last) 235 245 234 aa0280 note: high impedance, external pull-down resistor os1 (output) dso (output) (dsck input) os0 (output) (see note) (dso output) (dsi input) (see note) 241 239 240 241 236 237 aa1281 extal os0Cos1 (output) note: 1. valid when the ratio between extal frequency and clock frequency equals 1 2. high impedance, external pull-down resistor (note 2) (note 1) 242 243 aa0282
4-32 dsp56012 data sheet motorola on-chip emulation (once) timing figure 4-28. dsp56012 once dsck next command after read register timing figure 4-29. synchronous recovery from wait state figure 4-30. asynchronous recovery from wait state figure 4-31. asynchronous recovery from stop state dsck (input) (next command) 244 aa0283 t0, t2 t1, t3 extal dr (input) dso (output) 248 246 247 aa0284 dr (input) dso (output) 248 249 aa0285 dr (input) dso (output) 250 251 aa0286
on-chip emulation (once) timing motorola specifications 4-33
4-34 dsp56012 data sheet motorola on-chip emulation (once) timing
tqfp package description motorola packaging 5-1 part 5 packaging 5.1 pin-out and package information this sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in part 3, signal/connection descriptions, on page 3-1are allocated. the dsp56012 is available in a 100-pin thin quad flat pack (tqfp) package. 5.2 tqfp package description top and bottom views of the tqfp package are shown in figure 5-1 and figure 5-2 with their pin- outs. figure 5-1. dsp56012 thin quad flat pack (tqfp), top view orientation mark 1 26 (top view) 25 50 75 51 76 100 gpio7 gpio6 gnd d gpio5 gpio4 v ccd gpio3 gpio2 gnd d gpio1 gpio0 gnd q v ccq not connected not connected gnd a not connected v cca not connected not connected gnd a not connected not connected not connected v cca dr not connected not connected not connected not connected dsck/os1 dsi/os0 dso sdi0 sdi1 wsr gnd s v ccq gnd q sckr wst sckt v ccs sdo0 sdo1 sdo2 gnd s hreq ss /ha2 mosi/ha0 not connected not connected gnd a not connected not connected h7/pb7 h6/pb6 gnd h hoa2/pb10 v cch hoa1/pb9 hr/w /pb11 hen /pb12 v ccq gnd q hack /pb14 gnd h hoa0/pb8 h5/pb5 v cch h4/pb4 h3/pb3 gnd h h2/pb2 h1/pb1 v ccs modc/nmi modb/irqb moda/irqa reset miso/sda gnd s sck/scl extal v ccp pcap gnd p pinit gnd q v ccq plock not connected not connected not connected aci ado v cch gnd h horeq /pb13 h0/pb0 aa1282 dsp56012
5-2 dsp56012 data sheet motorola tqfp package description figure 5-2. dsp56012 thin quad flat pack (tqfp), bottom view orientation mark 1 26 (bottom view) 25 50 75 51 76 100 gpio7 gpio6 gnd d gpio5 gpio4 v ccd gpio3 gpio2 gnd d gpio1 gpio0 gnd q v ccq not connected not connected gnd a not connected v cca not connected not connected gnd a not connected not connected not connected v cca v ccs modc/nmi modb/irqb moda/irqa reset miso/sda gnd s sck/scl extal v ccp pcap gnd p pinit gnd q v ccq plock not connected not connected not connected aci ado v cch gnd h horeq /pb13 h0/pb0 dr not connected not connected not connected not connected dsck/os1 dsi/os0 dso sdi0 sdi1 wsr gnd s v ccq gnd q sckr wst sckt v ccs sdo0 sdo1 sdo2 gnd s hreq ss /ha2 mosi /ha0 not connected not connected gnd a not connected not connected h7/pb7 h6/pb6 gnd h hoa2/pb10 v cch hoa1/pb9 hr/w /pb11 hen /pb12 v ccq gnd q hack /pb14 gnd h hoa0/pb8 h5/pb5 v cch h4/pb4 h3/pb3 gnd h h2/pb2 h1/pb1 aa1283 dsp56012
tqfp package description motorola packaging 5-3 table 5-1. dsp56012 signals by pin number pin # signal name pin # signal name pin # signal name pin # signal name 1 not connected 26 h0/pb0 51 mosi/ha0 76 gpio7 2 not connected 27 horeq /pb13 52 ss /ha2 77 gpio6 3 gnd a 28 gnd h 53 hreq 78 gnd d 4 not connected 29 v cch 54 gnd s 79 gpio5 5 not connected 30 ado 55 sdo2 80 gpio4 6 h7/pb7 31 aci 56 sdo1 81 v ccd 7 h6/pb6 32 not connected 57 sdo0 82 gpio3 8 gnd h 33 not connected 58 v ccs 83 gpio2 9 hoa2/pb10 34 not connected 59 sckt 84 gnd d 10 v cch 35 plock 60 wst 85 gpio1 11 hoa1/pb9 36 v ccq 61 sckr 86 gpio0 12 hr/w /pb11 37 gnd q 62 gnd q 87 gnd q 13 hen /pb12 38 pinit 63 v ccq 88 v ccq 14 v ccq 39 gnd p 64 gnd s 89 not connected 15 gnd q 40 pcap 65 wsr 90 not connected 16 hack /pb14 41 v ccp 66 sdi1 91 gnd a 17 gnd h 42 extal 67 sdi0 92 not connected 18 hoa0/pb8 43 sck/scl 68 dso 93 v cca 19 h5/pb5 44 gnd s 69 dsi/os0 94 not connected 20 v cch 45 miso/sda 70 dsck/os1 95 not connected 21 h4/pb4 46 reset 71 not connected 96 gnd a 22 h3/pb3 47 moda/irqa 72 not connected 97 not connected 23 gnd h 48 modb/irqb 73 not connected 98 not connected 24 h2/pb2 49 modc/nmi 74 not connected 99 not connected 25 h1/pb1 50 v ccs 75 dr 100 v cca
5-4 dsp56012 data sheet motorola tqfp package description table 5-2. dsp56012 signals by name signal name pin # signal name pin # signal name pin # signal name pin # aci 31 gpio7 76 not connected 32 pb14 16 ado 30 h0 26 not connected 33 pcap 40 dr 75 h1 25 not connected 34 pinit 38 dsck 70 h2 24 not connected 71 plock 35 dsi 69 h3 22 not connected 72 reset 46 dso 68 h4 21 not connected 73 sck 43 extal 42 h5 19 not connected 74 sckr 61 gnd a 3 h6 7 not connected 89 sckt 59 gnd a 91 h7 6 not connected 90 scl 43 gnd a 96 ha0 51 not connected 92 sda 45 gnd d 78 ha2 52 not connected 94 sdi0 67 gnd d 84 hack 16 not connected 95 sdi1 66 gnd h 8 hen 13 not connected 97 sdo0 57 gnd h 17 hoa0 18 not connected 98 sdo1 56 gnd h 23 hoa1 11 not connected 99 sdo2 55 gnd h 28 hoa2 9 os0 69 ss 52 gnd p 39 horeq 27 os1 70 v cca 93 gnd q 15 hreq 53 pb0 26 v cca 100 gnd q 37 hr/w 12 pb1 25 v ccd 81 gnd q 62 irqa 47 pb2 24 v cch 10 gnd q 87 irqb 48 pb3 22 v cch 20 gnd s 44 miso 45 pb4 21 v cch 29 gnd s 64 moda 47 pb5 19 v ccp 41 gnd s 54 modb 48 pb6 7 v ccq 14 gpio0 86 modc 49 pb7 6 v ccq 36 gpio1 85 mosi 51 pb8 18 v ccq 63 gpio2 83 nmi 49 pb9 11 v ccq 88 gpio3 82 not connected 1 pb10 9 v ccs 50 gpio4 80 not connected 2 pb11 12 v ccs 58 gpio5 79 not connected 4 pb12 13 wsr 65 gpio6 77 not connected 5 pb13 27 wst 60
tqfp package description motorola packaging 5-5 figure 5-3. 100-pin thin quad flat pack (tqfp) mechanical information dim a min max 14.00 bsc millimeters a1 7.00 bsc b 14.00 bsc b1 7.00 bsc c 1.70 c1 0.05 0.20 c2 1.30 1.50 d 0.10 0.30 e 0.45 0.75 f 0.15 0.23 g 0.50 bsc j 0.07 0.20 k 0.50 ref r1 0.08 0.20 s 16.00 bsc s1 8.00 bsc u 0.09 0.16 v 16.00 bsc v1 8.00 bsc w 0.20 ref z 1.00 ref q q q q notes: 1. dimensions and tolerances per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.35. minimum space between protrusion and adjacent lead or protrusion 0.07. 1 2 3 --- 0 7 0 plating u j d f rotated 90 clockwise section ab-ab base metal l-m m 0.08 n t c2 c1 (k) (z) (w) gage plane view aa 0.05 e 0.25 1 q 2x rr1 q view y 4x 25 tips 4x 25 100 76 75 51 26 50 1 n 0.2 t l-m 3x a s a1 s1 b1 v1 b v n 0.2 t l-m m n l view aa c 0.08 t 3 q 4x t seating plane 2 q 4x 100x view y ab c l x = l, m, or n g x ab case 983-02 issue e 12 ref 12 ref
5-6 dsp56012 data sheet motorola ordering drawings 5.3 ordering drawings complete mechanical information regarding dsp56012 packaging is available by facsimile through motorola's mfax? system. call the following number to obtain information by facsimile: the mfax automated system requests the following information: ? the receiving facsimile telephone number including area code or country code ? the callers personal identification number (pin) note: for first time callers, the system provides instructions for setting up a pin, which requires entry of a name and telephone number. ? the type of information requested: instructions for using the system a literature order form specific part technical information or data sheets other information described by the system messages a total of three documents may be ordered per call. the dsp56012 100-pin tqfp package mechanical drawing is referenced as 983-02. (602) 244-6609(602) 244-6609
thermal design considerations motorola design considerations 6-1 part 6 design considerations 6.1 thermal design considerations an estimation of the chip junction temperature, t j , in c can be obtained from the equation: equation 1: where: t a = ambient temperature ?c r q ja = package junction-to-ambient thermal resistance ?c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: equation 2: where: r q ja = package junction-to-ambient thermal resistance ?c/w r q jc = package junction-to-case thermal resistance ?c/w r q ca = package case-to-ambient thermal resistance ?c/w r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. this model is most useful for ceramic packages with heat sinks; ninety percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. again, if the estimations obtained from r q ja do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. a complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: ? to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. ? to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. ? if the temperature of the package case (t t ) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (t j C t t )/p d . as noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, this value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a t j t a p d r q ja () + = r q ja r q jc r q ca + =
6-2 dsp56012 data sheet motorola electrical design considerations thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. hence, the new thermal metric, thermal characterization parameter or y jt , has been defined to be (t j C t t )/p d . this value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 6.2 electrical design considerations warning: this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v cc ). use the following list of recommendations to assure correct dsp operation: ? provide a low-impedance path from the board power supply to each v cc pin on the dsp and from the board ground to each gnd pin. ? use at least four 0.01C0.1 m f bypass capacitors positioned as close as possible to the four sides of the package to connect the v cc power source to gnd. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v cc and gnd pins are less than 0.5 in per capacitor lead. ? use at least a four-layer printed circuit board (pcb) with two inner layers for v cc and gnd. ? because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. this recommendation particularly applies to the address and data buses as well as the irqa , irqb , and nmi pins. maximum pcb trace lengths of 6 inches are recommended. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v cc and gnd circuits. ? all inputs must be terminated (i.e., not allowed to float) using cmos levels, except as noted in part 3,signal/connection descriptions, on page 3-1. ? take special care to minimize noise levels on the v ccp and gnd p pins. ? if multiple dsp56012 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices.
power consumption considerations motorola design considerations 6-3 6.3 power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors which effect current consumption are described in this section. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. current consumption is described by the following formula: equation 3: where:c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle the maximum internal current (i cci max) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typical operating conditions. for applications that require very low-current consumption: ? minimize the number of pins that are switching. ? minimize the capacitive load on the pins. ? connect the unused inputs to pull-up or pull-down resistors. ? disable unused peripherals. ? disable unused pin activity. example 6-1. current consumption for an i/o pin loaded with 50 pf capacitance, operating at 5.5 v, and with a 81 mhz clock, toggling at its maximum possible rate (20 mhz), the current consumption is: equation 4: i cvf = i5010 12 C 5.5 20 10 6 5.5ma ==
6-4 dsp56012 data sheet motorola power-up considerations example 6-2. current consumption test code: org p:reset jmp main org p:main movep #$180000,x:$fffd move #0,r0 move #0,r4 move #0,r5 move #$00ff,m0 move #$00ff,m4 nop rep #256 move r0,x:(r0)+ rep #256 mov r4,y:(r4)+ clr a move l:(r0)+,a rep #30 mac x0,y0,ax:(r0)+,x0 y:(r4)+,y0 move a,p:(r5) jmp tp1 tp1 nop jmp main 6.4 power-up considerations to power-up the dsp56012 properly, ensure that the following conditions are met: ? stable power is applied to the device according to the specifications in table 4-3 on page 4-2 (dc electrical characteristics). ? the external clock oscillator is active and stable. ? reset is asserted according to the specifications in table 4-7 on page 4-5 (reset, stop, mode select, and interrupt timing). ? the following input pins are driven to valid voltage levels: dr , pinit, moda, modb, and modc. care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on table 4-1 on page 4-1 (maximum ratings), at all phases of the power-up procedure. this may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip. at the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. this is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state.
host port considerations motorola design considerations 6-5 6.5 host port considerations careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected. the situation exists in the host interface. the following paragraphs present considerations for proper operation. 6.5.1 host programming considerations ? unsynchronized reading of receive byte registers when reading receive byte registers, rxh or rxl, the host program should use interrupts or poll the rxdf flag which indicates that data is available. this assures that the data in the receive byte registers will be stable. ? overwriting transmit byte registers the host program should not write to the transmit byte registers, txh or txl, unless the txde bit is set, indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers will transfer valid data to the hrx register. ? synchronization of status bits from dsp to host hc, horeq , dma, hf3, hf2, trdy, txde, and rxdf status bits are set or cleared from inside the dsp and read by the host processor. (refer to the users manual for descriptions of these status bits.) the host can read these status bits very quickly without regard to the clock rate used by the dsp, but the state of the bit could be changing during the read operation. generally, this is not a system problem, because the bit will be read correctly in the next pass of any host polling routine. however, if the host asserts hen for more than timing number 31, with a minimum cycle time of timing number 31 + 32, then these status bits are guaranteed to be stable. exercise care when reading status bits hf3 and hf2 as an encoded pair. if the dsp changes hf3 and hf2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. if the combination of hf3 and hf2 has significance, the host could read the wrong combination. therefore, read the bits twice and check for consensus. ? overwriting the host vector the host program should change the host vector register only when the host command bit (hc) is clear. this change will guarantee that the dsp interrupt control logic will receive a stable vector. ? cancelling a pending host command exception the host processor may elect to clear the hc bit to cancel the host command exception request at any time before it is recognized by the dsp. because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the dsp may execute the host command exception after the hc bit is cleared. for these reasons, the hv bits must not be changed at the same time that the hc bit is cleared. ? variance in the host interface timing the host interface (hi) may vary (e.g., due to the pll lock time at reset). therefore, a host which attempts to load (bootstrap) the dsp should first make sure that the part has completed its hi port programming (by setting the init bit in icr then polling it and waiting it to be cleared, then reading the isr or by writing the treq/ rreq together with the init and then polling init, isr, and the horeq pin).
6-6 dsp56012 data sheet motorola host port considerations 6.5.2 dsp programming considerations ? synchronization of status bits from host to dsp dma, hf1, hf0, and hcp, htde, and hrdf status bits are set or cleared by the host processor side of the interface. these bits are individually synchronized to the dsp clock. (refer to the users manual for descriptions of these status bits.) ? reading hf0 and hf1 as an encoded pair care must be exercised when reading status bits hf0 and hf1 as an encoded pair (i.e., the four combinations 00, 01, 10, and 11 each have significance). a very small probability exists that the dsp will read the status bits synchronized during transition. therefore, hf0 and hf1 should be read twice and checked for consensus.
motorola ordering information 7-1 part 7 ordering information consult a motorola semiconductor sales office or authorized distributor to determine product availability and to place an order. table 7-1. ordering information part supply voltage package type pin count frequency (mhz) order number dspb56012 5 v thin quad flat pack (tqfp) 100 95 xcb56012bu95 note: the dspb56012 includes factory-programmed rom containing support for dolby ac-3 with dvd specifications. the part can be used only by customers licensed for dolby ac-3. future products in the dsp56012 family will include other rom-based options. for additional information on future part development, or to request customer-specific rom-based support, call your local motorola semiconductor sales office or authorized distributor.
7-2 dsp56012 data sheet motorola
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